Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/34041
Title: MNFTL : an efficient flash translation layer for MLC NAND flash memory storage systems
Authors: Qin, Z
Wang, YI
Liu, DUO
Shao, Z 
Guan, Y
Keywords: Address mapping
Flash translation layer
Garbage collection
MLC NAND flash memory
Issue Date: 2011
Publisher: IEEE
Source: 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 5-9 June 2011, New York, NY, p. 17-22 How to cite?
Journal: 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 5-9 June 2011, New York, NY 
Abstract: The new write constraints of multi-level cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.
URI: http://hdl.handle.net/10397/34041
ISBN: 978-1-4503-0636-2
ISSN: 0738-100x
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