Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/32545
Title: Allocation of FPGA DSP-macros in multi-process high-level synthesis systems
Authors: Carrion Schafer, B 
Keywords: Digital signal processing chips
Field programmable gate arrays
High level synthesis
Macros
Issue Date: 2014
Publisher: IEEE
Source: 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 20-23 January 2014, Singapore, p. 616-621 How to cite?
Abstract: High-Level Synthesis (HLS) is a single process synthesis method that has shown to produce very good results compared to hand coded RTL, especially for DSP-related applications. At the same time FPGAs are reaching capacities that allow entire systems to be implemented on them. Most of these systems are also DSP-related and make intensive use of the FPGAs' embedded hardmacros (e.g. DSP-blocks). This works presents a method to efficiently allocate DSP-macros in multi-process systems created using HLS in order to minimize the overall area. The proposed method calculates the area sensitivity of each process when its multiply-accumulate (MAC) operations are either mapped onto the FPGA's hardmacro or its configurable resources and allocates the available hardmacros across all processes. Experimental results show that our method creates very good results compared to the optimal solution at a negligible running time.
URI: http://hdl.handle.net/10397/32545
ISBN: 
DOI: 10.1109/ASPDAC.2014.6742959
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