Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/32193
Title: PTL : PCM translation layer
Authors: Shao, Z 
Chang, N
Dutt, N
Keywords: PCM (Phase Change Memory)
Issue Date: 2012
Publisher: IEEE
Source: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 19-21 August 2012, Amherst, MA, p. 380-385 How to cite?
Abstract: PCM (Phase Change Memory) has been used as NOR flash replacement in embedded systems, and poses interesting system-level challenges for transparent exploitation of these memory structures by embedded systems software. We propose such a system-level transparent framework, called PTL (PCM Translation Layer), to efficiently manage PCM. PTL's translation layer conceals the physical constraints of the PCM architecture so that embedded systems software can use PCMs in a transparent manner, while efficiently exploiting the idiosyncrasies of the PCM architecture. We study the requirements for transparently managing PCM in embedded systems, and propose the system architecture of PTL. As a case study, we propose a simple yet effective wear leaveling technique by exploiting application-specific features in embedded systems. The experimental results show that our wear leveling technique can effectively improve the lifetime of PCM chips compared with the previous work. We expect this work can serve as a first step towards the full exploration of PCM in embedded systems.
URI: http://hdl.handle.net/10397/32193
ISBN: 978-1-4673-2234-8
ISSN: 2159-3469
DOI: 10.1109/ISVLSI.2012.75
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