Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/31763
Title: HW acceleration of multiple applications on a single FPGA
Authors: Liu, Y
Schafer, BC
Keywords: High-Level Synthesis
HW accelleration
Multi-Process
Issue Date: 2014
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014, 2014, 7082797, p. 284-285 How to cite?
Abstract: This works presents a fast and efficient method to map multiple computationally intensive kernels onto the same FPGA given the FPGA area and communication bandwidth constraint. FPGAs have grown to a size where multiple applications can now be mapped onto a single device. It is therefore important to develop methods than can efficiently decide which kernels of all of the applications under consideration should be mapped onto the FPGA in order to maximize the total system acceleration. Our method shows very good results compared to a standard genetic algorithm, which is often used for multi-objective optimization problems and against the optimal solution obtained using an exhaustive search method. Experimental results show that our method is very scalable and extremely fast.
Description: 13th International Conference on Field-Programmable Technology, FPT 2014, 10-12 December 2014
URI: http://hdl.handle.net/10397/31763
ISBN: 9.78E+12
DOI: 10.1109/FPT.2014.7082797
Appears in Collections:Conference Paper

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