Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/31594
DC FieldValueLanguage
dc.contributorDepartment of Electronic and Information Engineering-
dc.creatorWong, MWT-
dc.date.accessioned2015-09-30T09:42:52Z-
dc.date.available2015-09-30T09:42:52Z-
dc.identifier.isbn0-7695-1951-2-
dc.identifier.issn1081-7735-
dc.identifier.urihttp://hdl.handle.net/10397/31594-
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectCircuit testingen_US
dc.subjectDesign for testabilityen_US
dc.subjectFault diagnosisen_US
dc.titleIssues related to the formulation of DFT solution for analog circuit test using equivalent fault analysisen_US
dc.typeConference Paperen_US
dc.identifier.spage120-
dc.identifier.epage123-
dc.identifier.doi10.1109/ATS.2003.1250795-
dcterms.abstractThis paper identifies a few important points at which the application of equivalent fault analysis becomes the preferred choice in formulating a DFT solution for analog circuit test. These issues are important in that the test and/or design engineer should be aware of them in order to come up with effective test solutions to enhance fault diagnosis.-
dcterms.bibliographicCitation12th Asian Test Symposium, 2003 : ATS 2003, 16-19 November 2003, p. 120-123-
dcterms.issued2003-
dc.relation.ispartofbook12th Asian Test Symposium, 2003 : ATS 2003, 16-19 November 2003-
dc.identifier.rosgroupidr18161-
dc.description.ros2003-2004 > Academic research: refereed > Refereed conference paper-
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