Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/31487
Title: Testing embedded cores by weighted sum of selected node voltages
Authors: Ko, KY
Wong, MWT
Lee, YS
Keywords: VLSI
Built-in self test
Integrated circuit testing
Mixed analogue-digital integrated circuits
Issue Date: 2002
Publisher: IEEE
Source: Proceedings of the 19th IEEE Instrumentation and Measurement Technology Conference, 2002 : IMTC/2002, May 2002, v. 1, p. 595-599 How to cite?
Abstract: The utilization of re-useable Intellectual Property (IP) cores for System-on-Chip (SoC) design can shorten the time-to-market and thus reduce the design cost but on the other hand, the challenge of testing such embedded IP cores is initiated. This paper presents a Built-In Self-Test (BIST) technique based on the weighted sum of selected node voltages (WSSNV) for the effective testing of these embedded cores. The proposed BIST technique can greatly reduced the number of testing I/O pins and thus reduce the size and simplify the design of test architecture for SoC. Besides, testing time and procedure are reduced and simplified respectively since only one testing output is needed to be observed.
URI: http://hdl.handle.net/10397/31487
ISBN: 0-7803-7218-2
ISSN: 1091-5281
DOI: 10.1109/IMTC.2002.1006909
Appears in Collections:Conference Paper

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