Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/31204
Title: Address assignment sensitive variable partitioning and scheduling for DSPs with multiple memory banks
Authors: Xue, C
Liu, T
Shao, Z 
Hu, J
Jia, Z
Sha, E
Issue Date: 2008
Source: IEEE International Conference on Acoustics, Speech and Signal Processing, 2008 : ICASSP 2008, March 31 2008-April 4 2008, Las Vegas, NV, p. 1453-1456
Abstract: Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory access to be executed in parallel. Dedicated address generation units (AQUs) are commonly presented in DSPs to perform address arithmetic in parallel to the main datapath. Address assignment, optimization of memory layout of program variables to reduce address arithmetic instruction, has been studied extensively on single memory architecture. Make effective use of AQUs on multiple memory banks is a great challenge to compiler design and has not been studied previously. In this paper, we exploit address assignment with variable partitioning for scheduling on DSP architectures with multiple memory banks and AQUs. Our approach is built on novel graph models which capture both parallelism and serialism demands. An efficient scheduling algorithm, Address Assignment Sensitive Variable Partitioning (AASVP), is proposed to best leverage both multiple memory banks and AQUs. Experimental results show significant improvement compare to existing methods.
Keywords: Design Automation
Memory Management
Program Compilers
Scheduling
Publisher: IEEE
ISBN: 978-1-4244-1483-3
978-1-4244-1484-0 (E-ISBN)
ISSN: 1520-6149
DOI: 10.1109/ICASSP.2008.4517894
Appears in Collections:Conference Paper

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