Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/28591
Title: An ASIC design of a high-speed Clock and Data Recovery circuit
Authors: Ng, CW
Yu, KH
Sham, CW
Tse, CKM 
Keywords: Clock and Data Recovery
Phase lock loop
Voltage control oscillator
Issue Date: 2012
Publisher: Scientific.Net
Source: Advanced materials research, 2012, v. 403-408, p. 1218-1223 How to cite?
Journal: Advanced materials research 
Abstract: Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13μm standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.
Description: 2011 7th International Conference on MEMS, NANO and Smart Systems, ICMENS 2011, Kuala Lumpur, 4-6 November 2011
URI: http://hdl.handle.net/10397/28591
ISBN: 9783037853122
ISSN: 1022-6680
EISSN: 1662-8985
DOI: 10.4028/www.scientific.net/AMR.403-408.1218
Appears in Collections:Conference Paper

Access
View full-text via PolyU eLinks SFX Query
Show full item record

Page view(s)

58
Last Week
0
Last month
Citations as of Jun 17, 2018

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.