Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/27239
Title: SIAR : customized real-time interactive router for analog circuits$
Authors: Yao, H
Yang, F
Cai, Y
Zhou, Q
Sham, CW
Keywords: Analog routing
Global routing
Interactive routing
SIAR
Splitting graph
Issue Date: 2015
Publisher: Elsevier
Source: Integration, the VLSI Journal, 2015, v. 48, no. 1, p. 170-182 How to cite?
Journal: Integration, the VLSI Journal 
Abstract: As analog and mixed-signal (AMS) circuitry gains increasing portions in modern SoCs, automatic analog routing is becoming more and more important. However, routing for analog circuits has always been an extremely challenging task due to complicated electrical and geometrical constraints. Due to these constraints, current analog routers often fail to obtain a routing solution that the designer wants. To incorporate the designer's expertise during routing, a customized real-time interactive analog router is attracting increasing concerns in industry. This paper presents a fast customized real-time interactive analog router called SIAR. A key feature of SIAR is that it allows for real-time interactions between the router and the designer. The designer can try different guiding points by moving the cursor in the user window and SIAR will return and display the corresponding routing solution in real-time, such that the designer could choose the most satisfactory one. The guiding points are very important for the designer to obtain satisfactory routing solutions, even for routing solutions with analog matching constraints by setting symmetric guiding points. A new splitting graph based routing model is presented to efficiently search the routing path and record the number of turns/vias during searching by efficient tile splitting operations. SIAR supports different routing modes such as point-to-point, point-to-module and module-to-module. An efficient connecting point selection method is presented such that an optimal routing solution is preserved when connecting to a module. Different design rules such as variable wire and via width/spacing rules, along with the same-net spacing rules, are supported in SIAR. Moreover, a global routing stage is presented to speedup the routing process for large designs. Experimental results are promising.
URI: http://hdl.handle.net/10397/27239
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2014.03.001
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