Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/27207
Title: On reducing hidden redundant memory accesses for DSP applications
Authors: Wang, M
Shao, Z 
Xue, J
Keywords: Digital signal processing (DSP) applications
instruction scheduling
loop optimization
memory optimization
Issue Date: 2011
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on very large scale integration (VLSI) systems, 2011, v. 19, no. 6, 5451148, p. 997-1010 How to cite?
Journal: IEEE transactions on very large scale integration (VLSI) systems 
Abstract: Reducing memory accesses is particularly important for digital signal processing (DSP) applications since they are widely used in embedded systems and need to be executed with high performance and low power consumption. In this paper, we propose a machine-independent loop memory access optimization technique, redundant load exploration and migration (REALM), to explore hidden redundant load operations and migrate them outside loops based on loop-carried data dependence analysis. We implement REALM into IMPACT and Trimaran. To the best of our knowledge, this is the first work to implement the memory access reduction with loop-carried data reuse in real world compilers. We conduct experiments using a set of benchmarks from DSPstone and MiBench on the cycle-accurate VLIW simulator of Trimaran. The experimental results show that our technique significantly reduces the number of memory accesses.
URI: http://hdl.handle.net/10397/27207
ISSN: 1063-8210
EISSN: 1557-9999
DOI: 10.1109/TVLSI.2010.2043963
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