Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/25241
Title: Fast power- and slew-aware gated clock tree synthesis
Authors: Lu, J
Chow, WK
Sham, CW
Keywords: Clock gating
clock tree synthesis
design automation
Issue Date: 2012
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on very large scale integration (VLSI) systems, 2012, v. 20, no. 11, 6046234, p. 2094-2103 How to cite?
Journal: IEEE transactions on very large scale integration (VLSI) systems 
Abstract: Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power- and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In PSACTS, a more practical clock slew constraint is applied. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. The experimental results show that the power cost of our work is smaller and the runtime is reduced. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry.
URI: http://hdl.handle.net/10397/25241
ISSN: 1063-8210
EISSN: 1557-9999
DOI: 10.1109/TVLSI.2011.2168834
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