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Title: Switching-activity minimization on instruction-level loop for VLIW DSP applications
Authors: Shao, Z
Zhuge, Q
Liu, M
Xiao, B 
Sha, E
Keywords: Minimisation
Parallel architectures
Processor scheduling
Signal processing
Issue Date: 2004
Publisher: IEEE
Source: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors : proceedings : September 27-29, 2004, Galveston, Texas, p. 224-234 (CD-ROM) How to cite?
Abstract: This work develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (switching-activity minimization loop scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.
ISBN: 0-7695-2226-2
ISSN: 2160-0511
DOI: 10.1109/ASAP.2004.1342473
Appears in Collections:Conference Paper

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