Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/24344
Title: Design space minimization with timing and code size optimization for embedded DSP
Authors: Zhuge, Q
Shao, Z
Xiao, B 
Sha, E
Keywords: Digital signal processing chips
Integrated circuit design
Minimisation
Timing
Issue Date: 2003
Publisher: IEEE
Source: First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003, 1-3 October 2003, Newport Beach, CA, USA, p. 144-149 How to cite?
Abstract: One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integrated Framework for Design Optimization and Space Minimization (IDOM) towards finding the minimum configuration satisfying timing and code size constraints. We show an effective way to reduce the design space to be explored through the study of the fundamental properties and relations among multiple design parameters, such as retiming value, unfolding factor, timing, and code size. Theories are presented to produce a small set of feasible design choices with provable quality. IDOM algorithm is proposed to generate high-quality design by integrating performance and code size optimization techniques. The experimental results on a set of DSP benchmarks show the efficiency and effectiveness of the IDOM algorithm. It constantly generates the minimal configuration for all the benchmarks. The cost of design space exploration using IDOM is only 3% of that using the standard method.
URI: http://hdl.handle.net/10397/24344
ISBN: 1-58113-742-7
DOI: 10.1109/CODESS.2003.1275274
Appears in Collections:Conference Paper

Access
View full-text via PolyU eLinks SFX Query
Show full item record

Page view(s)

31
Last Week
1
Last month
Checked on Sep 17, 2017

Google ScholarTM

Check

Altmetric



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.