Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/23949
Title: Efficient multiplier structure for realization of the discrete cosine transform
Authors: Chau, LP
Siu, WC 
Keywords: Discrete cosine transform
Serial-Parallel multiplier algorithm
Issue Date: 2003
Source: Signal processing : image communication, 2003, v. 18, no. 7, p. 527-536 How to cite?
Journal: Signal Processing: Image Communication 
Abstract: This paper presents an efficient serial-parallel multiplier algorithm that realizes the input data bit-serially, for implementation of the discrete cosine transform (DCT), which realizes the input data bit-serially. First, the DCT equation is split into a few groups of equations by using some mathematical techniques, and index tables are constructed to facilitate efficient data permutations. A new formulation of the DCT is then derived. Second, we represent the cosine coefficient in binary form and realize multiplications using a new serial-parallel multiplier architecture that results in a simple structure for VLSI realization.
URI: http://hdl.handle.net/10397/23949
ISSN: 0923-5965
DOI: 10.1016/S0923-5965(03)00040-7
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