Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/23550
Title: High-level synthesis for DSP applications using heterogeneous functional units
Authors: Shao, Z
Zhuge, Q
Xue, C
Xiao, B 
Sha, E
Keywords: Digital signal processing chips
High level synthesis
Integrated circuit design
Scheduling
Issue Date: 2005
Publisher: IEEE
Source: Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005, 18-21 January 2005, v. 1, p. 302-304 How to cite?
Abstract: This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpose architecture synthesis, an important problem is how to assign a proper FV type to each operation of a DSP application and generate a schedule in such a way that all requirements can be met and the total cost can be minimized. In the paper, we propose a two-phase approach to solve this problem. In the first phase, we propose an algorithm to assign proper FU types to applications such that the total cost can be minimized while the timing constraint is satisfied. In the second phase, based on the assignments obtained in the first phase, we propose a minimum resource scheduling algorithm to generate a schedule and a feasible configuration that uses as little resource as possible. The experimental results show that our approach can generate high-performance assignments and schedules with great reduction on total cost compared with the previous work.
URI: http://hdl.handle.net/10397/23550
ISBN: 0-7803-8736-8
DOI: 10.1109/ASPDAC.2005.1466178
Appears in Collections:Conference Paper

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