Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/22093
Title: Parallel system design for time-delay neural networks
Authors: Zhang, D 
Pal, SK
Issue Date: 2000
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on systems, man, and cybernetics. Part C, Applications and reviews, 2000, v. 30, no. 2, p. 265-275 How to cite?
Journal: IEEE transactions on systems, man, and cybernetics. Part C, Applications and reviews 
Abstract: In this paper, we develop a parallel structure for the time-delay neural network used in some speech recognition applications. The effectiveness of the design is illustrated by 1) extracting a window computing model from the time-delay neural systems; 2) building its pipelined architecture with parallel or serial processing stages; and 3) applying this parallel window computing to some typical speech recognition systems. An analysis of the complexity of the proposed design shows a greatly reduced complexity while maintaining a high throughput rate.
URI: http://hdl.handle.net/10397/22093
ISSN: 1094-6977
DOI: 10.1109/5326.868447
Appears in Collections:Journal/Magazine Article

Access
View full-text via PolyU eLinks SFX Query
Show full item record

SCOPUSTM   
Citations

4
Last Week
0
Last month
0
Citations as of Aug 21, 2017

WEB OF SCIENCETM
Citations

4
Last Week
0
Last month
0
Citations as of Aug 20, 2017

Page view(s)

40
Last Week
0
Last month
Checked on Aug 20, 2017

Google ScholarTM

Check

Altmetric



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.