Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/21677
Title: Investigation on the use of GPGPU for fast sparse matrix factorization
Authors: Tian, Y
Zhou, B
Zhang, YT
Chan, KW 
Keywords: Sparse matrix factorization
GPU computing
GPGPU
CUDA
Issue Date: 2011
Publisher: Taylor & Francis
Source: Journal of international council on electrical engineering, 2011, v. 1, no. 1, p. 116-122 How to cite?
Journal: Journal of international council on electrical engineering 
Abstract: Solution for network equations is frequently encountered by power system researchers. With the increasingly larger system size, time consumed network solution is becoming a dominant factor in the overall time cost. One distinct and important feature of the network admittance matrix is that it is highly sparse, which need to be addressed by specialized computation techniques. One technique to accelerate matrix factorization is parallel computation, with which data processing can be divided into different tasks and implemented simultaneously. However, up to now, efficiency of parallel computation algorithm implemented on multi-processor systems is adversely affected by the data communication latency between processors. In this paper, by taking advantage of the parallel computing power of the contemporary Graphic Processing Units (GPU) and designs of sparse technique for matrix factorization implemented on GPU, proposed algorithms are implemented and evaluated on the Computer Unified Device Architecture (CUDA) interface of the NVIDIA GPU. Preliminary results show significant improvement of speed of LU factorization.
URI: http://hdl.handle.net/10397/21677
DOI: 10.5370/JICEE.2011.1.1.116
Appears in Collections:Journal/Magazine Article

Access
View full-text via PolyU eLinks SFX Query
Show full item record

Page view(s)

50
Last Week
2
Last month
Checked on Oct 23, 2017

Google ScholarTM

Check

Altmetric



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.