Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/214
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dc.contributorDepartment of Computing-
dc.creatorZhang, DD-
dc.creatorPal, SK-
dc.date.accessioned2014-12-11T08:27:11Z-
dc.date.available2014-12-11T08:27:11Z-
dc.identifier.issn1045-9227-
dc.identifier.urihttp://hdl.handle.net/10397/214-
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.rights© 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.rightsThis material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.subjectNeuro-fuzzy clusteringen_US
dc.subjectSystolic arrayen_US
dc.subjectVery large scale integration (VLSI)en_US
dc.titleA fuzzy clustering neural networks (FCNs) system design methodologyen_US
dc.typeJournal/Magazine Articleen_US
dc.identifier.spage1174-
dc.identifier.epage1177-
dc.identifier.volume11-
dc.identifier.issue5-
dc.identifier.doi10.1109/72.870048-
dcterms.abstractA system design methodology for fuzzy clustering neural networks (FCNs) is presented. This methodology emphasizes coordination between FCN model definition, architectural description, and systolic implementation. Two mapping strategies both from FCN model to system architecture and from the given architecture to systolic arrays are described. The effectiveness of the methodology is illustrated by: 1) applying the design to an effective FCN model; 2) developing the corresponding parallel architecture with special feedforward and feedback paths; and 3) building the systolic array (SA) suitable for very large scale integration (VLSI) implementation.-
dcterms.accessRightsopen accessen_US
dcterms.bibliographicCitationIEEE transactions on neural networks, Sept. 2000, v. 11, no. 5, p.1174-1177-
dcterms.isPartOfIEEE transactions on neural networks-
dcterms.issued2000-09-
dc.identifier.isiWOS:000089508300012-
dc.identifier.scopus2-s2.0-0034270238-
dc.identifier.rosgroupidr03505-
dc.description.ros2000-2001 > Academic research: refereed > Publication in refereed journal-
dc.description.oaVersion of Recorden_US
dc.identifier.FolderNumberOA_IR/PIRAen_US
dc.description.pubStatusPublisheden_US
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