Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/20411
Title: Testing system-on-chip by summations of cores' test output voltages
Authors: Ko, KY
Wong, MWT
Lee, YS
Keywords: Built-in self test
Fault diagnosis
Industrial property
Integrated circuit design
Integrated circuit testing
System-on-chip
Issue Date: 2002
Publisher: IEEE
Source: Proceedings of the 11th Asian Test Symposium, 2002 : ATS '02, 18-20 November 2002, p. 350-355 How to cite?
Abstract: The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.
URI: http://hdl.handle.net/10397/20411
ISBN: 0-7695-1825-7
ISSN: 1081-7735
DOI: 10.1109/ATS.2002.1181736
Appears in Collections:Conference Paper

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