Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/18941
Title: A layered QC-LDPC decoder architecture for high speed communication system
Authors: Sham, CW
Chen, X
Tam, WM
Zhao, Y
Lau, FCM 
Keywords: Channel coding
Cyclic codes
Decoding
Field programmable gate arrays
Parity check codes
Issue Date: 2012
Publisher: IEEE
Source: 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2-5 December 2012, Kaohsiung, p. 475-478 How to cite?
Abstract: The performance of a high-throughput long-distance communication system such as an optical transmission system is limited by the Net Coding Gain (NCG) of the Forward Error Correction (FEC) system. Summarizing the previous research works, Low-Density Parity-Check (LDPC) codes form one of the most promising FEC schemes to be applied in high-throughput communication systems. Designing a practical channel coding scheme with high code rate, low complexity, high throughput and extremely low error floor has always been a very challenging problem. Quasi-cyclic low-density parity-check (QC-LDPC) codes have been promising candidates to fulfill the above requirements but the implementation issues remain. In this paper, we propose a layered QC-LDPC decoder architecture with high code rate, low complexity, high throughput and excellent error performance. The architecture has been implemented using FPGA and the error performance has been shown to be good.
URI: http://hdl.handle.net/10397/18941
ISBN: 978-1-4577-1728-4
DOI: 10.1109/APCCAS.2012.6419075
Appears in Collections:Conference Paper

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