Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/18273
Title: Testing analogue and mixed-signal integrated circuits by weighted sum of selected node voltages
Authors: Ko, KY
Wong, MWT
Lee, YS
Issue Date: 2003
Publisher: Taylor & Francis Ltd
Source: International journal of electronics, 2003, v. 90, no. 5, p. 313-329 How to cite?
Journal: International Journal of Electronics 
Abstract: System-on-chip (SOC) design based on intellectual property (IP) cores has become a growing trend in integrated circuit (IC) design. Testing of such cores is a challenging problem, especially when these cores are deeply embedded in the system chip. The wrapper of the P1500 standard can facilitate the testing of such cores; however, a full-size wrapper is expensive because the hardware overhead is large. If the requirement for testing I/O pins of IP cores is considered and reduced to a minimum during the core design, SOC designers will need to put much less effort into testing the cores. In this paper, a built-in self-test (BIST) technique, which is applicable to both analogue and mixed-signal integrated circuits and is based on the weighted sum of selected node voltages, is proposed. Besides high fault coverage, the proposed BIST technique needs only one extra testing output pin, and only a single dc stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for testing IP cores.
URI: http://hdl.handle.net/10397/18273
ISSN: 0020-7217
DOI: 10.1080/00207210310001610547
Appears in Collections:Journal/Magazine Article

Access
View full-text via PolyU eLinks SFX Query
Show full item record

Page view(s)

30
Last Week
1
Last month
Checked on Aug 13, 2017

Google ScholarTM

Check

Altmetric



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.