Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/16378
Title: Congestion prediction in early stages of physical design
Authors: Sham, CW
Young, EFY
Lu, J
Keywords: Estimation
Floorplanning
Placement
Issue Date: 2009
Publisher: Association for Computing Machinary
Source: ACM transactions on design automation of electronic systems, 2009, v. 14, no. 1, 12 How to cite?
Journal: ACM transactions on design automation of electronic systems 
Abstract: Routability optimization has become a major concern in physical design of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominant factor of the overall performance of a circuit. In order to optimize interconnect cost, we need a good congestion estimation method to predict routability in the early designing stages. Many congestion models have been proposed but there's still a lot of room for improvement. Besides, routers will perform rip-up and reroute operations to prevent overflow, but most models do not consider this case. The outcome is that the existing models will usually underestimate the routability. In this paper, we have a comprehensive study on our proposed congestion models. Results show that the estimation results of our approaches are always more accurate than the previous congestion models.
URI: http://hdl.handle.net/10397/16378
ISSN: 1084-4309
DOI: 10.1145/1455229.1455241
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