Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/1575
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dc.contributorDepartment of Electrical Engineering-
dc.creatorDing, K-
dc.creatorCheng, KWE-
dc.creatorXue, X-
dc.creatorDivakar, BP-
dc.creatorWang, SX-
dc.creatorXu, C-
dc.creatorWang, DH-
dc.date.accessioned2014-12-11T08:26:31Z-
dc.date.available2014-12-11T08:26:31Z-
dc.identifier.isbn978-988-17471-3-6-
dc.identifier.urihttp://hdl.handle.net/10397/1575-
dc.language.isoenen_US
dc.publisherPower Electronics Research Centre, The Hong Kong Polytechnic Universityen_US
dc.rightsCopyright © The Hong Kong Polytechnic University 2009.en_US
dc.subjectVoltage sagen_US
dc.subjectPower interruptionen_US
dc.subjectPower systemen_US
dc.subjectDiode-Clampeden_US
dc.subjectMultilevelen_US
dc.titleA novel single-phase voltage sag restorer with diode-clamped multilevel bridgeen_US
dc.typeConference Paperen_US
dc.description.otherinformationAuthor name used in this publication: K. Dingen_US
dc.description.otherinformationAuthor name used in this publication: K. W. E. Chengen_US
dc.description.otherinformationAuthor name used in this publication: X. D. Xueen_US
dc.description.otherinformationAuthor name used in this publication: C. D. Xuen_US
dcterms.abstractA novel single-phase voltage sag restorer with diode-clamped multilevel bridge is presented. In the proposed circuit, traditional two-level half bridge inverter is replaced by multilevel diode-clamped inverter, in which the dc-bus voltage is split into several levels by series-connected bulk capacitors. Although the multilevel circuit has more component count than the two-level circuit it is more suitable for high voltage applications. The restorer is bypassed under normal operating conditions and is connected to the load depending upon voltage sag detection. The switches of the inverter are controlled by PWM signals. In the paper the operation of the multilevel circuit is simulated in SABER to study the operating capability of the multilevel inverter. A comparative study between the traditional two-level circuit and the proposed multilevel circuit is provided to highlight the performance of the multilevel circuit.-
dcterms.accessRightsopen accessen_US
dcterms.bibliographicCitationPESA 2009 : International Conference on Power Electronic Systems and Applications : 20th-22nd May 2009, p. [1-6]-
dcterms.issued2009-
dc.identifier.isiWOS:000273501600022-
dc.identifier.scopus2-s2.0-70350439573-
dc.relation.ispartofbookPESA 2009 : International Conference on Power Electronic Systems and Applications : 20th-22nd May 2009-
dc.description.oaVersion of Recorden_US
dc.identifier.FolderNumberOA_IR/PIRAen_US
dc.description.pubStatusPublisheden_US
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