Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/15228
Title: Loop scheduling with complete memory latency hiding on multi-core architecture
Authors: Xue, C
Shao, Z 
Liu, M
Qiu, M
Sha, E
Keywords: Processor scheduling
Program control structures
Storage management
Issue Date: 2006
Publisher: IEEE
Source: 12th International Conference on Parallel and Distributed Systems, 2006 : ICPADS 2006, July 2006, Minneapolis, MN, p. 8 How to cite?
Abstract: The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new loop scheduling with memory management technique, iterational retiming with partitioning (IRP), that can completely hide memory latencies for applications with multi-dimensional loops on architectures like CELL processor (J.A. Kahle et al., 2005). In IRP, the iteration space is first partitioned carefully. Then a two-part schedule, consisting of processor and memory parts, is produced such that the execution time of the memory part never exceeds the execution time of the processor part. These two parts are executed simultaneously and complete memory latency hiding is reached. Experiments on DSP benchmarks show that IRP consistently produces optimal solutions as well as significant improvement over previous techniques
URI: http://hdl.handle.net/10397/15228
ISBN: 0-7695-2612-8
ISSN: 1521-9097
DOI: 10.1109/ICPADS.2006.58
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