Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/14678
Title: Optimizing address assignment and scheduling for DSPs with multiple functional units
Authors: Xue, C
Shao, Z 
Zhuge, Q
Xiao, B 
Liu, M
Sha, EHM
Keywords: Address assignment
Address generation unit (AGU)
Digital signal processor (DSP)
Multiple functional units (FUs)
Scheduling
Issue Date: 2006
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on circuits and systems. II, Express briefs, 2006, v. 53, no. 9, p. 976-980 How to cite?
Journal: IEEE transactions on circuits and systems. II, Express briefs 
Abstract: Digital signal processors provide dedicated address generation units (AGUs) that are capable of performing address arithmetic in parallel to the main data path. Address assignment, optimization of memory layout of program variables to reduce address arithmetic instructions by taking advantage of the capabilities of AGUs, has been studied extensively for single-functional-unit (FU) processors. In this brief, we exploit address assignment and scheduling for multiple-FU processors. We propose an efficient address assignment and scheduling algorithm for multipIe-FU processors. Experimental results show that our algorithm can greatly reduce schedule length and address operations on multiple-FU processors compared with the previous work.
URI: http://hdl.handle.net/10397/14678
ISSN: 1549-7747
EISSN: 1558-3791
DOI: 10.1109/TCSII.2006.880026
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