Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/13869
Title: Optimizing wirelength and routability by searching alternative packings in floorplanning
Authors: Sham, CW
Young, EFY
Zhou, H
Keywords: Floorplanning
Wirelength reduction
Issue Date: 2008
Publisher: Association for Computing Machinary
Source: ACM transactions on design automation of electronic systems, 2008, v. 13, no. 1, 21 How to cite?
Journal: ACM transactions on design automation of electronic systems 
Abstract: Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative packings. If a packing contains a rectangular bounding box of a group of modules, we can rearrange the blocks in the bounding box to obtain a new floorplan with the same area, but possibly with a smaller interconnect cost. Experimental results show that we can reduce the interconnect cost of a packing without any penalty in area.
URI: http://hdl.handle.net/10397/13869
ISSN: 1084-4309
DOI: 10.1145/1297666.1297687
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