Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/13857
Title: Constructing high-rate scale-free LDPC codes
Authors: Zheng, X
Lau, FCM 
Tse, CK 
Issue Date: 2010
Source: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 2010, 5537734, p. 3781-3784 How to cite?
Abstract: Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the "pure" SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes.
Description: 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, 30 May-2 June 2010
URI: http://hdl.handle.net/10397/13857
ISBN: 9781424453085
DOI: 10.1109/ISCAS.2010.5537734
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