Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/13325
Title: Loop scheduling with memory access reduction under register constraints for DSP applications
Authors: Wang, M
Liu, DUO
Wang, YI
Shao, Z 
Keywords: Processor scheduling
Memory management
Issue Date: 2009
Publisher: IEEE
Source: IEEE Workshop on Signal Processing Systems, 2009 : SiPS 2009, 7-9 October 2009, Tampere, p. 139-144 How to cite?
Abstract: In embedded systems, high-performance DSP needs to be performed not only with high-data throughput but also with low-power consumption. In this paper, we propose an effective scheduling framework, MARLS (Memory Access Reduction Loop Scheduling), to reduce memory accesses for DSP applications with loops. In the framework, we generate register operations to replace redundant load operations, and schedule these operations while allocating available physical registers to their register operands. We implement our technique into the Trimaran compiler and conduct experiments using a set of benchmarks from DSPstone and MiBench on the cycle-accurate VLIW simulator of Trimaran. The experimental results show that our technique significantly reduces the number of memory accesses.
URI: http://hdl.handle.net/10397/13325
ISBN: 978-1-4244-4335-2
978-1-4244-4335-2 (E-ISBN)
ISSN: 1520-6130
DOI: 10.1109/SIPS.2009.5336239
Appears in Collections:Conference Paper

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