Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/12820
Title: Performance analysis of caching effect on packet processing in a multi-threaded processor
Authors: Ju, M
Che, H
Wang, Z
Keywords: Cache storage
Multi-threading
Real-time systems
Software performance evaluation
Issue Date: 2009
Publisher: IEEE
Source: WRI International Conference on Communications and Mobile Computing, 2009 : CMC '09, 6-8 January 2009, Yunnan, p. 412-416 How to cite?
Abstract: In this paper, we aim at analyzing how effective the caching technique is, in dealing with real-time packet processing through simulation studies. First of all, we introduce a fast multithreaded processor simulator. The simulator is applied to emulate the basic IP forwarding using Intel IXP1200 with the addition of caching. Our simulation results indicate that overall, caching can be an effective means to improve packet processing performance. However, we also note that, for large cache miss rates (e.g., 27.2%), caching can be ineffective, especially under stringent delay/loss constraints, and/or high time locality for cache misses. Our simulation results also indicate that the effectiveness of caching is sensitive to the actual delay/loss constraint. We also analyzed the reasons for these results in details. These observations provide significant insight as to how many threads should be configured in a processor where caching is employed to hide the memory access latency.
URI: http://hdl.handle.net/10397/12820
ISBN: 978-0-7695-3501-2
DOI: 10.1109/CMC.2009.247
Appears in Collections:Conference Paper

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