Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/12263
Title: Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors
Authors: Wang, M
Wang, Y
Liu, D
Qin, Z
Shao, Z 
Keywords: DSP applications
Leakage power
Loop scheduling
VLIW architecture
Issue Date: 2010
Publisher: Elsevier
Source: Journal of systems and software, 2010, v. 83, no. 5, p. 772-785 How to cite?
Journal: Journal of systems and software 
Abstract: As feature size shrinks, leakage energy consumption has become an important concern. In this paper, we develop a compiler-assisted instruction-level scheduling technique to reduce leakage energy consumption for applications with loops on VLIW architecture. In the proposed technique, we obtain the schedule with minimum leakage energy from the ones that are generated by repeatedly regrouping a loop based on rotation scheduling and bipartite-matching. We conduct experiments on a set of benchmarks from DSPstone, Mediabench, Netbench, and MiBench based on the power model of the VLIW processors. The results show that our algorithm can achieve significant leakage energy saving compared with the previous work.
URI: http://hdl.handle.net/10397/12263
ISSN: 0164-1212
DOI: 10.1016/j.jss.2009.11.727
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