Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/11218
Title: Influence of the interface charges' location on the threshold voltage of pMOSFET
Authors: Cao, K
He, W
Zhao, XJ
Cao, JM
Issue Date: 2014
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014, 2014, 7021280 How to cite?
Abstract: The effect of the interface charges' location variation on the threshold voltage of pMOS device was numerically simulated. By dividing the interface into several regions, the relationship between that interface charges and the threshold voltage drift is well revealed combining the drain biasing conditions. In addition, we also investigated the mechanism of threshold voltage variation by comparing the surface potentials of various models. The study was helpful in pinpointing the critical device location where interface charges are more effective, which may promote the research on Drain Bias-Negative Bias Temperature Instability (DB-NBTI) effects.
Description: 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014, Guilin, 28-31 October 2014
URI: http://hdl.handle.net/10397/11218
ISBN: 9781479932962
DOI: 10.1109/ICSICT.2014.7021280
Appears in Collections:Conference Paper

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