Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/10935
DC FieldValueLanguage
dc.contributorDepartment of Electronic and Information Engineering-
dc.creatorKo, KY-
dc.creatorWong, MWT-
dc.date.accessioned2015-09-30T09:42:20Z-
dc.date.available2015-09-30T09:42:20Z-
dc.identifier.isbn0-7695-0887-1-
dc.identifier.issn1081-7735-
dc.identifier.urihttp://hdl.handle.net/10397/10935-
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectAnalogue circuitsen_US
dc.subjectBuilt-in self testen_US
dc.subjectBuilt-in self-testen_US
dc.titleNew built-in self-test technique based on addition/subtraction of selected node voltagesen_US
dc.typeConference Paperen_US
dc.identifier.spage39-
dc.identifier.epage43-
dc.identifier.doi10.1109/ATS.2000.893600-
dcterms.abstractFor a faulty circuit, the sensitivity of different node voltages with respect to different faults is not the same. To make use of the node voltages to detect and/or isolate faults, access to the internal circuit nodes is required. Techniques like voltage scan can be adopted to achieve this put-pose but considerable hardware overhead are incurred. Practically, not all of the circuit nodes are necessary to achieve the maximum fault coverage. In this paper we propose a new built-in self-test (BIST) technique, making use of the addition/subtraction of a small pre-selected set of circuit node voltages to achieve high fault detection and location while hardware overhead is small when compared with the voltage scan approaches-
dcterms.bibliographicCitationProceedings of the Ninth Asian Test Symposium, 2000 : ATS 2000, December 2000, Taipei, p. 39-43-
dcterms.issued2000-
dc.relation.ispartofbookProceedings of the Ninth Asian Test Symposium, 2000 : ATS 2000, December 2000, Taipei-
dc.identifier.rosgroupidr03034-
dc.description.ros2000-2001 > Academic research: refereed > Refereed conference paper-
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