Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/10935
Title: New built-in self-test technique based on addition/subtraction of selected node voltages
Authors: Ko, KY
Wong, MWT
Keywords: Analogue circuits
Built-in self test
Built-in self-test
Issue Date: 2000
Publisher: IEEE
Source: Proceedings of the Ninth Asian Test Symposium, 2000 : ATS 2000, December 2000, Taipei, p. 39-43 How to cite?
Journal: Proceedings of the Ninth Asian Test Symposium, 2000 : ATS 2000, December 2000, Taipei 
Abstract: For a faulty circuit, the sensitivity of different node voltages with respect to different faults is not the same. To make use of the node voltages to detect and/or isolate faults, access to the internal circuit nodes is required. Techniques like voltage scan can be adopted to achieve this put-pose but considerable hardware overhead are incurred. Practically, not all of the circuit nodes are necessary to achieve the maximum fault coverage. In this paper we propose a new built-in self-test (BIST) technique, making use of the addition/subtraction of a small pre-selected set of circuit node voltages to achieve high fault detection and location while hardware overhead is small when compared with the voltage scan approaches
URI: http://hdl.handle.net/10397/10935
ISBN: 0-7695-0887-1
ISSN: 1081-7735
DOI: 10.1109/ATS.2000.893600
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