Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/10566
Title: Real-time loop scheduling with leakage energy minimization for embedded VLIW DSP processors
Authors: Wang, M
Shao, Z 
Xue, C
Sha, E
Keywords: Computational complexity
Digital signal processing chips
Leakage currents
Multiprocessing systems
Processor scheduling
Issue Date: 2007
Publisher: IEEE
Source: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2007 : RTCSA 2007, 21-24 August 2007, Daegu, p. 12-19 How to cite?
Abstract: In this paper, we develop a novel real-time instruction-level loop scheduling technique to reduce leakage energy consumption for applications with loops on VLIW architecture. We first prove that the scheduling problem with the minimum leakage energy consumption within a timing constraint is NP-complete. Then, LEMLS (leakage energy minimization loop scheduling) algorithm is designed to repeatedly regroup a loop based on rotation scheduling (Chao et al., 1997), and decrease leakage energy integrating with leakage power reduction mechanism. We conduct experiments on a set of DSP benchmarks based on the power model of the VLIW processors in (Liao et al., 2002). The results show that our algorithm achieves significant leakage energy saving compared with list scheduling and the algorithm in (You et al., 2006).
URI: http://hdl.handle.net/10397/10566
ISBN: 978-0-7695-2975-2
ISSN: 1533-2306
DOI: 10.1109/RTCSA.2007.60
Appears in Collections:Conference Paper

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