Back to results list
Please use this identifier to cite or link to this item:
|Title:||Test methodologies for analogue cores of system-on-chip|
|Keywords:||Systems on a chip -- Testing|
Integrated circuits -- Very large scale integration
Metal oxide semiconductors, Complementary
Hong Kong Polytechnic University -- Dissertations
|Publisher:||The Hong Kong Polytechnic University|
|Abstract:||Three built-in self-test (BIST) techniques were developed during this research project. These testing techniques are: Weighed Sum of Selected Node Voltages (WSSNV), Summations of Cores' Test Output Voltages (SOCTOV) and Full Range Window Comparator (FRWC) BIST techniques. The first one is proposed for the effective testing of embedded analogue cores while the later two are proposed for that of the analogue portion of System-On-Chip (SOC). All these BIST techniques have the major advantages of high fault coverage, small hardware overhead and fast test application time.|
The WSSNV BIST technique makes use of the weighted sum of a pre-selected small set of circuit node voltages to detect faults. When compared with the voltage scan approach, the WSSNV BIST technique is verified to have higher fault coverage while at the same time hardware overhead is much less. It needs only an extra pin for testing output and a single DC stimulus is needed to feed at the primary input of the circuit (or core) under test (CUT). Studies have been carried out to apply the proposed BIST technique to an analogue active low pass filter; a mixed-signal threshold detector of a telephone ringer IC; and a simulated mathematical functional block of a SOC to verify its effectiveness and efficiency. Test architecture of the WSSNV BIST technique for embedded cores is also proposed.
SOCTOV BIST technique is a unified BIST approach to SOC testing that is based on weighted and non-weighted sums of cores' test output voltages. It is developed in conjunction with the WSSNV BIST technique. Under test mode, all the test output voltages of the cores are summed together (weighted and non-weighted). By observing these weighted and non-weighted summing outputs and those known nominal values, the faulty condition of the SOC and the location of the faulty core can be uniquely identified. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique
FRWC BIST technique is based on Window Comparator of Cores' Test Output Voltages for the effective testing of embedded analogue cores. This BIST technique is also developed in conjunction with the WSSNV BIST technique. The resultant testing response is a binary bit stream which can be easily incorporated with the existing testing technique for the digital portion of the SOC such that a single digital Automatic Test Equipment (ATE) is all that required for the testing of a mixed-signal SOC. By reading the bit steam of the testing response, the health status of the SOC, location of the faulty core(s), and even the faults within the faulty core(s) can be identified. In contrast with the SOCTOV BIST technique, it has the major advantage of the capability to locate the unique faults (or equivalent fault sets) within the faulty core(s).
|Description:||xii, 96 leaves : ill. ; 30 cm.|
PolyU Library Call No.: [THS] LG51 .H577M EIE 2003 Ko
|Rights:||All rights reserved.|
|Appears in Collections:||Thesis|
Show full item record
Files in This Item:
|b17330798_link.htm||For PolyU Users||167 B||HTML||View/Open|
|b17330798_ir.pdf||For All Users (Non-printable)||2.35 MB||Adobe PDF||View/Open|
Checked on Mar 26, 2017
Checked on Mar 26, 2017
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.