Please use this identifier to cite or link to this item: http://hdl.handle.net/10397/10483
Title: Optimized address assignment with array and loop transformations for minimizing schedule length
Authors: Xue, CJ
Jia, Z
Shao, Z 
Wang, M
Sha, EHM
Keywords: Array
Arrays
Delay
Digital signal processor (DSP)
Not given
Processor scheduling
Program processors
Registers
Schedules
Scheduling
Issue Date: 2008
Publisher: Institute of Electrical and Electronics Engineers
Source: IEEE transactions on circuits and systems. I, Regular papers, 2008, v. 55, no. 1, p. 379-389 How to cite?
Journal: IEEE transactions on circuits and systems. I, Regular papers 
Abstract: Reducing address arithmetic operations by optimization of address offset assignment greatly improves the performance of digital signal processor (DSP) applications. However, minimizing address operations alone may not directly reduce code size and schedule length for DSPs with multiple functional units. Little research work has been conducted on loop optimization with address offset assignment problem for architectures with multiple functional units. In this paper, we combine loop scheduling, array interleaving, and address assignment to minimize the schedule length and the number of address operations for loops on DSP architectures with multiple functional units. Array interleaving is applied to optimize address assignment for arrays in loop scheduling process. An algorithm, Address Operation Reduction Rotation Scheduling (AORRS), is proposed. The algorithm minimizes both schedule length and the number of address operations. with to list scheduling, AORRS shows an average reduction of 38.4% in schedule length and an average reduction of 31.7% in the number of address operations. Compared with rotation scheduling, AORRS shows an average reduction of 15.9% in schedule length and 33.6% in the number of address operations.
URI: http://hdl.handle.net/10397/10483
ISSN: 1549-8328
EISSN: 1558-0806
DOI: 10.1109/TCSI.2007.913721
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